This invention relates to method and apparatus for decoding PCM digital input words, and more particularly to an integrated PCM decoder which is substantially insensitive to parasitic and stray capacitance effects.
PCM encoders and/or decoders are described in the articles "A Two-Chip PCM Voice Codec With Filters" by Y. A. Hakque, et al., IEEE Journal of Solid State Circuits, Vol. SC-14, No. 6, pages 961-969, December 1979; "A PCM Voice Codec With On-Chip Filters" by J. T. Caves, et al., IEEE Journal of Solid State Circuits, Vol. SC-14, No. 1, pages 65-73, February 1979; "A Segmented Mu-255 Law PCM Encoder Utilizing NMOS Technology" by Paul R. Gray, et al., IEEE Journal of Solid State Circuits, Vol. SC-11, No. 6, pages 740-747, December 1976; and "A Unified Formulation of Segment Companding Laws and Synthesis of Codecs and Digital Compandors" by H. Kaneko, The Bell System Technical Journal (BSTJ), September 1970, pages 1555-1588, which are incorporated herein by reference. Mu-law decoders operating on 8-bit PCM code words have employed arrays of binary weighted capacitors, the total array capacitance typically being 255 times the capacitance of the smallest capacitance of the array. The capacitances of the two largest binary weighted capacitors of the array are therefore 128 and 64 times that of the smallest capacitor thereof. In integrated circuit structures it is desirable to minimize the surface area of a chip that is required for individual circuit elements. It is readily seen that the chip area dedicated for integrated capacitors in such an integrated decoder may be reduced by approximately 50% by deleting only one of the binary weighted capacitors. An integrated decoder requiring a capacitance of only 32 times that of the smallest capacitor of an array is disclosed in copending patent application (infra).
An object of this invention is the provision of an improved PCM decoder requiring only three equal valued capacitors.